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Lattice Semiconductor
Convolutional Encoder File Hierarchy
Table 3. File Hierarchy
File Name
Parameter Files
conv_enco_o4_1_00x_params.v
Core Files
conv_enco_o4_1_00x.ngo
conv_enco_o4_1_00x.prf
conv_enco_xp_1_00x.ld2
Verilog Instantiation Templates
ce_wrap.v
conv_enco_o4_1_00x.v
Testbench Files
tb_ce_wrap_fsim.v
Convolutional Encoder User’s Guide
Description
All con?gurable parameters
Core database ?le for ORCA ? Series 4 devices.
Core preference ?le for ORCA Series 4 devices.
Core database ?le for ispXPGA? devices
Verilog user design template for synthesis
Verilog synthesis model for the core
Testbench for RTL simulation
IPexpress
The Lattice IP con?guration tool, IPexpress, is incorporated in the ispLEVER ? software. IPexpress includes a GUI
for entering the required parameters to con?gure the core. For more information on using IPexpress and the
ispLEVER design software, refer to the software help and tutorials included with ispLEVER. For more information
on ispLEVER, see the Lattice web site at: www.latticesemi.com/software.
Figure 9. Convolutional Encoder Parameter Con?guration Dialog Box
Implementing a Convolutional Encoder Core Design
Black Box Consideration
Since the core is delivered as a gate-level netlist, the synthesis software will not re-synthesize the internal nets of
the core. In the synthesis process, the instantiated core must be declared as a black box. The ispLEVER software
automatically detects the provided netlist of the instantiated IP core in the design. For more detailed information
regarding Synplify’s black box declaration, please refer to the Instantiating Black Boxes in Verilog section of the
Synplify reference manual.
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